1. Field of the Invention
The present invention relates to a semiconductor device having an SOI (Silicon On Insulator) structure and a manufacturing method thereof, and particularly to a semiconductor device having an isolation insulating film with its bottom surface not reaching a buried oxide film (hereinafter, referred to as a xe2x80x9cpartial STI (Shallow Trench Isolation)xe2x80x9d), and a manufacturing method thereof.
2. Description of the Background Art
A semiconductor device having an SOI structure including a semiconductor substrate, a buried oxide film, and a semiconductor layer is configured such that active regions are surrounded by the buried oxide film and an element isolation with its bottom surface reaching the buried oxide film (hereinafter, referred to as a xe2x80x9cfull STI (Shallow Trench Isolation)xe2x80x9d). Such a semiconductor device has advantages that even if CMOS transistors are formed, there is no fear of occurrence of latchup; since the source/drain regions are in contact with the buried oxide film, a junction capacitance is smaller than that of a semiconductor device in which transistors are directly formed on the surface of a semiconductor substrate, to enable high-speed operation; and since the leakage current upon stand-by becomes smaller, the power consumption can be suppressed.
According to the above semiconductor device, however, if the thickness of the semiconductor layer formed on the surface of the buried oxide film is as larger as 0.15 xcexcm or more, carriers generated by impact ionization phenomenon (holes for an nMOS, and electrons for a pMOS) are accumulated in a portion, under a channel formation region, of the semiconductor layer, so that kink occurs, the operational breakdown voltage is degraded, or the potential of the channel region is made unstable, thereby causing various problems due to the substrate floating effect, such as the dependence of delay time on frequency. As a result, in general, the potential of each channel formation region is fixed. Japanese Patent Laid-open No. Sho 58-124243 discloses a semiconductor device in which the potential of each channel formation region is fixed as described above.
In recent years, a structure has been known, for example, from IEEE International SOI Conference, October 1997, in which isolation by the partial STI is performed not to fix potentials of channel formation regions for each transistor but to collectively fix potentials of channel formation regions of a plurality of transistors having the same conduction type, thereby realizing the micro-structure of the semiconductor device.
FIG. 26 is a top view of a conventional semiconductor device. In the figure, reference numeral 104 designates an isolation insulating film; 106 is a gate electrode; 107 and 108 are source/drain regions, and 109 is a wiring line. As shown in the figure, in the case of adopting the partial STI, the wiring line 109 for fixing the potential of channel formation regions is formed so as to accord with a plurality of transistors having the same conduction type.
FIG. 27 is a sectional view, taken on line Xxe2x80x94X of FIG. 26, of the conventional semiconductor device. In the figure, reference numeral 101 designates a semiconductor substrate; 102 is a buried oxide film; 1010 is a channel formation region; 105 is a gate insulating film; 103 is a semiconductor layer; and 1011 is a channel stopper layer. As shown in the figure, the isolation insulating film 104 between two adjacent transistors does not reach the buried oxide film 102, and the channel stopper layer 1011 heavily containing an impurity having the same conduction type as that of the channel formation region 1010 is formed under the isolation insulating film 104. The two channel formation regions 1010 are connected to each other via the channel stopper layer 1011, and are connected to the wiring line 109. In this way, the potentials of the channel formation regions 1010 are fixed.
The partial STI structure, however, is low in between-element isolation breakdown voltage. As a result, if a differential potential occurs between source/drain regions adjacent to each other via the channel stopper layer by, for example, applying a source voltage to one of wiring lines (not shown) connected to the source/drain regions of the adjacent transistors and applying a drain voltage to the other, a relatively large leakage current may flow in the channel stopper layer. To solve such an inconvenience, the between-element isolation width must be set at a large value, thereby obstructing formation of a micro-structure of the semiconductor device.
FIG. 28 is a sectional view, taken on line Yxe2x80x94Y of FIG. 26, of the conventional semiconductor device. As is apparent from the figure, since the isolation insulating film 104 between the source/drain regions of the adjacent transistors does not reach the buried oxide film 102, a leakage current may flow between the source/drain regions via the channel stopper layer 1011.
An object of the present invention is to provide a semiconductor device including an isolation insulating film having a partial STI structure capable of collectively fixing voltages applied to channel formation regions of a plurality of transistors, characterized by suppressing a leakage current flowing through a channel stopper layer provided under the isolation insulating film, thereby improving the isolation characteristic and breakdown voltage, and to provide a method of manufacturing the semiconductor device.
The above objects of the present invention are achieved by a semiconductor device including an SOI substrate composed of a semiconductor substrate, a buried oxide film, and a semiconductor layer. The semiconductor device includes an isolation insulating film formed in such a manner as to surround first and second active regions arranged on a principal surface of said semiconductor layer and to be separated a specific distance from said buried oxide film. The device also includes a first active element formed in said first active region as well as a second active element formed in said second active region. An impurity layer is formed between said buried oxide film and one principal plane of said semiconductor substrate. Further, a wiring line is electrically connected to said impurity layer.
The above objects of the present invention are achieved by a method of manufacturing a semiconductor device. In the method, an impurity layer is formed on the surface of a semiconductor substrate of an SOI substrate having a semiconductor layer formed on the surface of said semiconductor layer via a buried oxide film. An isolation insulating film is formed in such a manner as that said isolation insulating film surrounds first and second active regions arranged on the surface of said buried oxide film and a portion of said semiconductor layer remains under said isolation insulating film. A first active element is formed in said first active region. A second active element is formed in said second active region. Further, a wiring line connected to said impurity layer is formed.
The above objects of the present invention are also achieved by a method of manufacturing a semiconductor device. In the method, a mask is formed for covering the surfaces of first and second active regions arranged on a buried oxide film of an SOI substrate having a semiconductor layer formed on the surface of a semiconductor substrate via said buried oxide film. The semiconductor layer is etched downwardly from a principal surface thereof by using said mask in such a manner that a bottom portion of said semiconductor layer remains, to form a trench surrounding said first and second active regions. Ions of an impurity are implanted in a portion, under said trench, of said semiconductor substrate, to form an impurity layer on the surface of said semiconductor substrate. An insulating film is formed over the entire surface. A portion, on the surface of said mask, of said insulating film is removed before the mask is removed. A first active element is formed in said first active region. A second active element is formed in said second active region. Further, a wiring line connected to said impurity layer is formed.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.